1. Field of the Invention
The present invention relates to a semiconductor device having a trench-type isolation structure and a method of manufacturing the same.
2. Description of the Background Art
In a semiconductor integrated circuit, in order to completely independently control elements in its operation, it is necessary to eliminate electrical interference between the elements. For this reason, an isolation structure having an isolation region is adopted in the semiconductor integrated circuit. As one of the isolation structures, a trench isolation method is widely known and various improvements thereof are proposed.
The trench isolation method is a method to electrically insulate the elements by forming a trench which extends from a surface of a substrate towards the inside thereof and filling the inside of the trench with a dielectric substance. In this method, there is little bird""s beak, which is found in the isolation structure formed by the LOCOS method. For this reason, the isolation structure by the trench isolation method needs a smaller area on the surface of the substrate to form than that by the LOCOS method, and therefore the trench isolation method is a preferable method to promote size reduction of the semiconductor integrated circuit. Accordingly, the trench isolation method is an essential isolation method in the semiconductor integrated circuit whose size is to be further reduced in the future.
FIG. 23 is a schematic plan (top) view showing a semiconductor device 101P in the background art. FIGS. 24 and 25 are (vertical) cross sections taken along the line APxe2x80x94AP and the line BPxe2x80x94BP in FIG. 23a respectively. FIG. 26 is an enlarged cross section showing part of FIG. 25. In FIG. 23, part of the elements shown in FIGS. 24 to 26 are omitted.
As shown in FIGS. 23 to 26, the semiconductor device 101P comprises a P-type silicon single crystal substrate (hereinafter, referred to simply as xe2x80x9csubstratexe2x80x9d) 1P. A trench 2P is formed, extending from a main surface 1SP of the substrate 1P towards the inside of the substrate 1P, and the trench 2P forms an isolation region AR2P.
A silicon oxide film 9AP is formed on an inner surface 2SP of the trench 2P and a silicon oxide film 9BP is formed on the silicon oxide film 9AP. In this case, the inside of the trench 2P is filled with the silicon oxide films 9AP and 9BP (also generally referred to as xe2x80x9csilicon oxide film 9Pxe2x80x9d). The silicon oxide film 9P is a so-called trench isolation.
In the background-art semiconductor device 101P, the silicon oxide film 9P which serves as the trench isolation has a shape sagging from the main surface 1SP of the substrate 1P along an opening edge of the trench 2P (hereinafter, also referred to as xe2x80x9csag or depressionxe2x80x9d) 9RP.
An N channel-type field effect transistor (NMOSFET) is formed in an active region AR1P of the semiconductor device 101P. In more detail, a gate insulating film 4P extends on the main surface 1SP of the substrate 1P across the active region AR1P (see FIG. 23). A polysilicon film 5AP and a tungsten silicide film 5BP are layered on the gate insulating film 4P in this order, and the polysilicon film 5AP and the tungsten silicide film 5BP form a gate electrode 5P. Further, as shown in FIGS. 25 and 26, the gate electrode 5P extends also on the silicon oxide film 9P across the silicon oxide film 9P and is also arranged in the sag 9RP of the silicon oxide film 9P. A sidewall oxide film 41P is formed on the gate insulating film 4P, being in contact with a side surface of the gate electrode 5P.
Further, two source/drain layers 6P are formed in the main surface 1SP of the substrate 1P with a channel region of the MOSFET below the gate electrode 5P interposed therebetween. The source/drain layers 6P consists of an N+-type layer 6BP and an Nxe2x88x92-type layer 6AP, and the Nxe2x88x92-type layer 6AP has an impurity concentration lower than that of the N+-type layer 6BP and is formed closer to the channel region.
Furthermore, a channel impurity layer 10P to control a threshold voltage of the MOSFET is formed in the main surface 1SP of the substrate 1P. The channel impurity layer 10P is formed of a P-type layer like the substrate 1P and has an impurity concentration higher than that of the substrate 1P. The channel impurity layer 10P is provided in a region deeper than the channel region and the whole of it is formed in a plane substantially parallel to the main surface 1SP of the substrate 1P. Part of the channel impurity layer 10P and part of the source/drain layers 6P share a formation region (overlap one another) in the substrate 1P, and more specifically, the channel impurity layer 10P is formed across bottom portions of the source/drain layers 6P.
Next, a method of manufacturing the semiconductor device 101P will be discussed, referring to FIGS. 27 to 31 along with FIGS. 23 to 26. Further, FIGS. 27 to 31 are vertical cross sections taken along the line APxe2x80x94AP of FIG. 23, like FIG. 24.
First, the substrate 1P is prepared, and the main surface 1SP of the substrate 1P is thermally oxidized to form a silicon oxide film 7P (see FIG. 27). Subsequently, a silicon nitride film 8P (see FIG. 27) is formed on the silicon oxide film 7P.
Next, a resist (not shown) to cover a region other than the region which is to be the isolation region is formed on the silicon nitride film 8P by photolithography technique. Then, by anisotropic etching with the resist used as a mask, the silicon nitride film 8P, the silicon oxide film 7P and the sub 1P is partially etched in this order. With this etching, a trench 2aP is formed, extending from an exposed surface of the silicon nitride film 8P to the inside of the substrate 1P as shown in FIG. 27. After that, the inner surface 2SP of the trench 2aP is thermally oxidized to form a silicon oxide film 9AaP as shown in FIG. 28, and subsequently a silicon oxide film 9BaP is so de posited as to cover the whole surface of the substrate 1P on the side of the main surface 1SP to fill the inside of the trench 2aP by the HDP (High Density Plasma)-CVD (Chemical Vapor Deposition) method.
The silicon oxide film 9BaP is polished until the silicon nitride film 8P is exposed by the CMP (Chemical Mechanical Polishing) method with the silicon nitride film 8P used as a stopper (see FIG. 29). With this polishing, the portion of the silicon oxide film 9BaP existing in the trench 2aP remains as the silicon oxide film 9BbP.
Then, the silicon nitride film 8P is removed with thermal phosphoric acid and subsequently the silicon oxide film 7P is removed with hydrofluoric acid (see FIG. 30). With these removing processes, the trench 2P which is part of the trench 2aP existing in the substrate 1P remains. Further, as shown in FIG. 30, in the process using the hydrofluoric acid, the sag 9RP is formed in the silicon oxide films 9AaP and 9BbP along an opening edge of the trench 2P.
Next, the main surface 1SP of the substrate 1P is thermally oxidized to form a silicon oxide film again. Then, the channel impurity layer 10P is formed by ion implantation as shown in FIG. 31. Subsequently, the silicon oxide film is removed with the hydrofluoric acid. At this time, the silicon oxide films 9AaP and 9BbP is partially etched to form the silicon oxide film 9P consisting of the silicon oxide films 9AP and 9BP, but the sag 9RP is formed or enlarged in this process using the hydrofluoric acid.
After that, the silicon oxide film, the polysilicon film and the tungsten silicide film are sequentially formed and patterned to form the gate insulating film 4P and the gate electrode 5P (see FIGS. 24 and 25). The ion implantation to form the Nxe2x88x92-type layer 6AP, formation of the sidewall oxide film 41P and the ion implantation to form the N+-type layer 6BP are sequentially performed to complete the semiconductor device 101P shown in FIGS. 23 to 25.
As discussed above, the semiconductor device 101P has the sag 9RP in the opening edge of the silicon oxide film 9P serving as the trench isolation. Specifically, in the background-art method of manufacturing the semiconductor device 101P, the silicon oxide films 9AaP and 9BbP is also partially etched and the sag 9RP is formed in the silicon oxide film 9P when the silicon oxide film 7P and the silicon oxide film which is formed again after removing the silicon oxide film 7P are removed with hydrofluoric acid (see FIGS. 29 to 31).
As shown in FIG. 26, since the sag 9RP is formed lower than the main surface 1SP of the substrate 1P, a portion of the gate electrode 5P which is formed in the sag 9RP is closer to the side surface of the trench 2P as compared with a case where no sag 9RP is formed. For this reason, an electric field E on the side surface of the trench 2P or the active region AR1P among the electric field caused by a voltage applied to the gate electrode 5 becomes strong. In other words, the electric field E is concentrated on an edge of the active region.
Since such an electric field concentration deteriorates the potential at the edge of the active region, the threshold voltage at the edge of the active region of the MOSFET is lower than that in the channel region (central portion). Specifically, a parasitic MOSFET (or parasitic element) having a threshold voltage lower than a desired (designed) voltage is formed at the edge of the active region. For this reason, the parasitic MOSFET turns on first in the operation, and then portions other than the parasitic MOSFET turn on. As a result, as indicated by the characteristic line xcex2 in the view of FIG. 32 showing the characteristics of the MOSFET, a drain current of the MOSFET starts to flow at a voltage lower the desired threshold voltage. In other words, a hump is observed in the characteristic view.
Further, when the channel width decreases as the size of the device is reduced, the presence of the parasitic MOSFET causes an inverse-narrow channel effect where the threshold voltage decreases as the channel width decreases. In other words, a current starts to flow at a voltage lower than the desired threshold voltage in the MOSFET due to the inverse-narrow channel effect.
Furthermore, even in a case of no sag 9RP, the electric field from various wires and the like formed in the isolation region AR2P or on the silicon oxide film 9P affects the potential at the edge of the active region through the silicon oxide film 9P or through the side surface of the trench 2P, to possibly form the parasitic MOSFET.
Since the hump and the inverse-narrow channel effect due to the presence of the parasitic MOSFET causes an increase in off current or leak current of the MOSFET, the yield of the semiconductor device 101P is disadvantageously lowered.
Further, though no sag is formed in the LOCOS because of difference in the method of forming the isolation structure, the trench isolation structure is essential for further size reduction of the semiconductor device, as discussed earlier.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a substrate having a main surface and including a semiconductor material of a predetermined conductivity type which has a predetermined impurity concentration; a trench formed extending from the main surface of the substrate towards the inside of the substrate; a dielectric substance formed in the trench, serving as a trench isolation; a first impurity layer having the same conductivity type as the predetermined conductivity type of the substrate and an impurity concentration higher than the predetermined impurity concentration of the substrate and extending in the substrate, being opposed to the main surface of the substrate; and a second impurity layer having a conductivity type opposite to the predetermined conductivity type of the substrate, formed in a portion inside the main surface of the substrate, and in the semiconductor device of the first aspect, the first impurity layer includes a first portion; and a second portion continuous with the first portion, extending deeper than the first portion from the main surface of the substrate, and part of the first portion of the first impurity layer is formed in the second impurity layer.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first portion of the first impurity layer is provided along a side surface of the trench.
According to a third aspect of the present invention, in the semiconductor device of the first or second aspect, the first portion of the first impurity layer is provided near an opening edge of the trench in the substrate.
According to a fourth aspect of the present invention, the semiconductor device of any one of the first to third aspects further comprises: a third impurity layer having the same conductivity type as the second impurity layer has, formed in another portion inside the main surface of the substrate without being in contact with the second impurity layer, and in the semiconductor device of the fourth aspect, another part of the first portion of the first impurity layer which is different from the part is formed in the third impurity layer, and the semiconductor device of the fourth aspect further comprises: a field effect transistor including the second impurity layer and the third impurity layer as source/drain layers, respectively.
According to a fifth aspect of the present invention, in the semiconductor device of the fourth aspect, the field effect transistor includes a gate insulating film formed on the main surface of the substrate; and a gate electrode extending over the gate insulating film and the dielectric substance.
The present invention is also directed to a method of manufacturing a semiconductor device. According to a sixth aspect of the present invention, the method of manufacturing a semiconductor device comprises the steps of: (a) preparing a substrate including a predetermined semiconductor material and having a predetermined conductivity type; (b) forming an oxide film including an oxide of the predetermined semiconductor material on the substrate to have a predetermined film thickness; (c) forming a semiconductor film including the predetermined semiconductor material on the oxide film; (d) partially etching the semiconductor film, the oxide film and the substrate in this order to form a trench which extends from the semiconductor film towards the inside of the substrate; (e) oxidizing surfaces of the substrate and the semiconductor film which are exposed in the trench to make an edge portion of the oxide film along the trench thicker than the predetermined film thickness; and (f) implanting an impurity of the same conductivity type as the predetermined conductivity type into the substrate through the oxide film after the step (e).
According to a seventh aspect of the present invention, in the method of the sixth aspect, the impurity implanted in the step (f) has a distribution in a direction of depth of the substrate with its peak near an interface between the edge portion which becomes thicker in the step (e) and the substrate.
According to an eighth aspect of the present invention, the method of the sixth or seventh aspect further comprises the step of: (g) performing a rapid thermal annealing on the substrate after the step (f).
According to a ninth aspect of the present invention, the method of any one of the sixth to eighth aspects further comprises the step of: (h) removing the semiconductor film by isotropic etching.
In the semiconductor device of the first aspect of the present invention, in a portion of the second impurity layer where part of the first portion of the first impurity layer is arranged, the impurity concentration of the second impurity layer can be lowered. Therefore, a depletion layer formed in a junction face between the second impurity layer and the substrate is likely to be widened near this portion, the junction capacitance can be reduced. Since this reduces the junction capacitance in the whole junction face, it is possible to improve an operating speed which is low due to large junction capacitance.
In the semiconductor device of the second aspect of the present invention, the first portion of the first impurity layer is provided along the side surface of the trench. Considering that the electric field from wires and the like arranged on the dielectric substance in the trench affects a potential of the substrate from the side surface of the trench, the first portion can compensate the characteristic feature near the trench. This reduces the problems in operation of the semiconductor device due to the electric field.
In the semiconductor device of the third aspect of the present invention, the first portion of the first impurity layer is provided near the opening edge of the trench. Anyway, the above electric field from the wires on the dielectric substance becomes stronger as it is closer to the wires and the like, in other words, closer to the opening edge of the trench. In this case, since the first portion of the first impurity layer is provided in a portion where the above electric field is stronger, it is possible to reliably reduce the problems in operation due to the above electric field.
In the semiconductor device of the fourth aspect of the present invention, since the second impurity layer and the third impurity layer (equivalent to the second impurity layer) serve as the source/drain layers of the field effect transistor, the operation of the field effect transistor, accordingly, the operation of the semiconductor device can be made faster.
In the semiconductor device of the fifth aspect of the present invention, it is possible to reduce the leak current by suppressing the hump and the inverse-narrow channel effect in the field effect transistor. As a result, the field effect transistor, accordingly, the semiconductor device can operate with desired (designed) characteristics. Further, in a case of DRAM (Dynamic Random Access Memory) including the field effect transistor, it is possible to suppress the loss of electric charges accumulated in a capacitor of the DRAM through the above reduction in leak current.
In the method of the sixth aspect of the present invention, in the oxidation step (e), the edge portion of the oxide film is made thicker than the initial state (in the step (b)). Therefore, even if the substrate is exposed by wet-etching the oxide film in the later step, with the thicker portion (edge portion) of the oxide film, it is possible to avoid formation of sag near the opening edge of the trench. Accordingly, it is possible to suppress formation of parasitic elements due to the presence of the sag and reduce the problems in operation of the semiconductor device.
Further, the impurity can be implanted shallower through the thicker portion (edge portion) of the oxide film than through a portion having an initial film thickness. Therefore, since the impurity can be implanted closer to the main surface of the substrate (the surface in contact with the oxide film) through the thicker portion than the portion having the initial film thickness near the trench, it is possible to increase the impurity concentration near the trench as compared with the initial impurity concentration of the substrate. The characteristic feature near the trench can be compensated with this high-concentration region and this can reduce the problems in operation of the semiconductor device due to the electric field from wires and the like arranged on the dielectric substance in the trench.
Moreover, in the step (f), the depth of impurity implantation can be easily controlled by implanting the impurity through the oxide film after the step (e). In other words, it is not necessary to implant the impurity in different steps with resists formed in order to change the implantation depth.
As the result of these effects, it is possible to manufacture the semiconductor device which can operate with desired characteristics at good yield.
In the method of the seventh aspect of the present invention, the concentration of the impurity in the substrate can become higher near the opening edge. Therefore, it is possible to reliably reduce the problems in operation due to the above electric field.
In the method of the eighth aspect of the present invention, it is possible to anneal out the point defect in the crystal caused by implantation of the impurity. Further, it is possible to suppress TED (Transient Enhanced Diffusion) in the later heat treatment and therefore the impurity can have a desired distribution. Accordingly, it is possible to reliably manufacture the semiconductor device which can exert the same effects as the methods of the sixth and seventh aspects.
In the method of the ninth aspect of the present invention, it is possible to avoid the damage at the anisotropic etching. Further, the whole of the semiconductor film can be easily removed with etching remainders reduced.
An object of the present invention is to provide a semiconductor device capable of operating with desired characteristics with formation of parasitic element in an active region suppressed, and a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.